The invention relates to a method for controlling a data driver in a manner dependent on a provided bit sequence and to a circuit configuration for carrying out the method. The method and configuration according to the invention is preferably used for transmiting binary-coded information between a memory and an information-processing device.
A main factor limiting the performance of computers at present is the transmission rate of memory information between a memory device and the processor. While processors today achieve clock frequencies, and consequently transmission rates, of 800 MHz, for technical reasons the frequencies for the data exchange between the processor or controller and the memory are several times lower (they are currently around 100 to at most 133 MHz). The data exchange takes place by transmitting binary data signals which, in the times between successive reference clock pulse edges, assume a xe2x80x9chighxe2x80x9d or a xe2x80x9clowxe2x80x9d level, depending on the binary value of the bits of a provided bit sequence which represents the information to be exchanged. An upper and a lower threshold value are generally defined for the data signal, the level being regarded as xe2x80x9cvalidxe2x80x9d when the threshold value is reached, and will be referred to here as the high or low xe2x80x9cvalidity levelxe2x80x9d.
Due to the unavoidable response time which a driver sending the data signal requires to complete the full level difference between the high level and the low level, the data signal at the output of the driver only reaches its respective validity level after a certain delay following a change of the input signal, which usually takes place with the reference clock pulse edge. One of the limiting factors for the operating frequency of clocked dynamic memory devices (SDRAMs, Synchronous Dynamic Random Access Memories) is the access time, i.e. the time from the reference clock pulse edge, which enables the data item at the output, until the validity level is reached at the output.
It is accordingly an object of the invention to provide a method for controlling a data driver and a corresponding configuration which overcome the above-mentioned disadvantages of the heretofore-known methods and configurations of this general type and which shorten the aforementioned access time.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for controlling a data driver, the method includes the steps of:
activating a data driver in dependence of a provided bit sequence for producing, at a data output of the data driver, a data signal such that the data signal, in time periods between periodic reference clock pulse edges, is in each case driven to one of a high validity level and a low validity level in accordance with a binary value of bits of the provided bit sequence, the high validity level being higher than the low validity level;
providing a preparation interval of a fixed length directly before selected reference clock pulse edges such that, during the preparation interval, the data driver is prompted to drive the data output of the data driver to a medium level provided between the high validity level and the low validity level, the selected reference clock pulse edges including a first reference clock pulse edge and at least all reference clock pulse edges occurring between data items of different binary values; and
providing the fixed length of the preparation interval such that the fixed length of the preparation interval is at least equal to a response time required by the data driver to drive the data output of the data driver over a level difference between one of the low and high validity levels and the medium level, and such that the fixed length of the preparation interval is shorter than twice the response time.
In other words, a method for controlling or activating a data driver in a manner dependent on a provided bit sequence, to produce at the data output of the driver a data signal which, in the times between periodic reference clock pulse edges, is in each case driven to a high or low validity level in accordance with the binary value of the bits of the provided bit sequence, is characterized according to the invention by the following features: a predetermined time period after a clock pulse edge, a preparation interval of a fixed length is defined, during which the driver is made to drive its data output to a medium level between the high validity level and the low validity level. The length of the preparation interval is made at least equal to the response time which the driver requires to drive its data output over the level difference between the one or the other validity level and the medium level; however, the preparation interval is made shorter than twice this response time. The selected reference clock pulse edges are at least the first reference clock pulse edge and all those reference clock pulse edges which lie between data items of different binary values.
According to the invention, the activation of the driver is consequently operated with xe2x80x9canticipationxe2x80x9d, in that, even before the reference clock pulse edges, the output is already driven in each case to a medium level, from which only half the full excursion or level difference remains to be covered. This shortens the time from the reference clock pulse edge to reaching the validity level at the output. This measure is carried out immediately before the first data item and before at least those data items which require level switching. The setting of the preparation interval to at least the response time applicable to half the excursion is intended to ensure with certainty that the output has reached the medium level at the time of the reference clock pulse edge. The restriction of the length of the preparation interval to at most twice this response time is intended to ensure that this interval does not begin before the validity of the current data item is reached. The shorter the preparation interval is within these set limits, the longer the holding time (period of validity) of the data items.
The anticipation or lead according to the invention can be achieved in two different ways. On the one hand, the output can be switched specifically to the medium level during a preparation interval before the delivery of each new data item, for example by switching the amplifier to high output impedance with the output connected via a resistor to a source of the medium level. In many customary bus systems today, terminable drivers which allow switching to high output impedance are used in any case. In this procedure, the access time is improved by the fact that, in the worst case (new data item is inverse to the previous item), only half the output excursion has to be covered, i.e. the access time is shortened by half the rise time of the driver (if this is scaled linearly with the driving input excursion, which does not necessarily have to be the case).
As the second possibility, a genuine xe2x80x9cprefetchxe2x80x9d can be used, in that it is determined in advance whether and in which direction the output must change in the case of the next data item in order if appropriate to start a correspondingly directed switching operation earlier, i.e. at the beginning of the preparation interval preceding the next data item. Here, too, the medium level is reached at the output at the latest at the next reference clock pulse edge, and consequently the access time for the next data item is shortened. This prefetch of course requires prior knowledge of the binary value of the next data item, that is to say simultaneous (or at least partly contemporaneous) provision of the current bit and the following bit. This can be realized very easily, for example by using a shift register receiving the bit sequence, which in many cases is present anyway. This is because many modules, in particular memory devices, generate a to-be-sent bit sequence extremely quickly or even in parallel and write it to a shift register in parallel for clock-pulse controlled onward transfer.
According to another feature of the invention, a switchable data driver is used as the data driver such that the data driver, in dependence of applied activation signals, is switchable between three switching states, the data output of the data driver being at or above the high validity level when the data driver is in a first one of the three switching states, the data output of the data driver being at or below the low validity level when the data driver is in a second one of the three switching states, and the data output of the data driver being at the medium level when the data driver is in a third one of the three switching states; at the latest from a start of the preparation interval provided before the first reference clock pulse edge and during a duration of each further preparation interval, an activation signal bringing about the third one of the switching states is applied; and with each reference clock signal edge preceding a data item of a first binary value, an activation signal bringing about the first one of the switching states is applied, and, with each reference clock pulse edge preceding a data item of a second binary value, an activation signal bringing about the second one of the switching states is applied.
According to another mode of the invention, the selected reference clock pulse edges further include reference clock pulse edges provided between data items of a same binary value.
According to yet another mode of the invention, the selected reference clock pulse edges only include the first reference clock pulse edge and reference clock pulse edges between data items of different binary values.
A further mode of the method according to the invention includes the step of using a switchable data driver as the data driver such that the data driver, in dependence of applied activation signals, is switchable between three switching states, the data output of the data driver being at or above the high validity level when the data driver is in a first one of the three switching states, the data output of the data driver being at or below the low validity level when the data driver is in a second one of the three switching states, and the data output of the data driver being at the medium level when the data driver is in a third one of the three switching states; applying, at the latest from a start of the preparation interval provided before the first reference clock pulse edge, an activation signal bringing about the third one of the switching states; applying, from a start of preparation intervals provided directly before a respective reference clock pulse edge preceding a data item of a first binary value, an activation signal bringing about the first one of the switching states; and applying, from a start of preparation intervals provided directly before a respective reference clock pulse edge preceding a data item of a second binary value, an activation signal bringing about the second one of the switching states.
Yet a further mode of the method according to the invention includes the step of using a switchable data driver as the data driver such that the data driver, in dependence of applied activation signals, is switchable between two switching states, the data output of the data driver being at or above the high validity level when the data driver is in a first one of the two switching states, the data output of the data driver being at or below the low validity level when the data driver is in a second one of the two switching states; applying, from a start of preparation intervals provided directly before a respective reference clock pulse edge preceding a data item of a first binary value, an activation signal bringing about the first one of the switching states; and applying, from a start of preparation intervals provided directly before a respective reference clock pulse edge preceding a data item of a second binary value, an activation signal bringing about the second one of the switching states.
With the objects of the invention in view there is also provided, a circuit configuration, including:
a data driver including an amplifier with a data input and a tristate output as a data output, the tristate output being switchable into a state of high output impedance by a deactivation signal;
a termination resistor connected to the data output;
a source for providing a medium level lying between a first validity level and a second validity level;
the data output of the data driver being connected, via the termination resistor to the source providing the medium level;
an activation circuit connected to the data input of the amplifier, the activation circuit responding to reference clock pulse edges and to bits of a provided bit sequence, the activation circuit supplying an activation signal to the data input of the amplifier such that, when reference clock pulse edges respectively preceding a data item of a first binary value occur, the activation signal goes to a level driving the data output to the first validity level and, when the reference clock pulse edges respectively preceding a data item of a second binary value occur, the activation signal goes to a level driving the data output to the second validity level; and
the activation circuit including a deactivating device applying a deactivation signal to the data driver for a duration of a respective preparation interval provided directly before given ones of the reference clock pulse edges such that, during the preparation interval, the data driver drives the data output to a medium level provided between the first validity level and the second validity level, the given ones of the reference clock pulse edges including a first reference clock pulse edge and at least all reference clock pulse edges between data items of different binary values, and wherein the preparation interval has a fixed length at least equal to a response time required by the data driver to drive the data output over a level difference between one of the first and second validity levels and the medium level, and wherein the fixed length of the preparation interval is shorter than twice the response time.
With the objects of the invention in view there is also provided, a circuit configuration, including:
a data driver including an amplifier with a data input and a tristate output as a data output, the tristate output being switchable into a state of high output impedance by a deactivation signal;
a termination resistor connected to the data output;
a source for providing a medium level lying between a high validity level and a low validity level, the high validity level being higher than the low validity level;
the data output of the driver being connected, via the termination resistor to the source providing the medium level;
a buffer memory for simultaneously providing a current bit of a bit sequence and a directly following bit of the bit sequence;
an activation circuit connected to the data input of the amplifier, the activation circuit responding to reference clock pulse edges and to the current bit and the directly following bit of the bit sequence for supplying an activation signal, the activation circuit supplying the activation signal such that, from a start of a preparation interval preceding a data item of a first binary value to a start of a following preparation interval, the activation signal has a level driving the data output to the high validity level and such that, from a beginning of a preparation interval preceding a data item of a second binary value to a start of a following preparation interval, the activation signal has a level driving the data output to the low validity level; and
the activation circuit including a deactivating device for supplying the deactivation signal, the deactivating device supplying the deactivation signal to the data driver from the start of a preparation interval preceding a first one of the reference clock pulse edges until the first one of the reference clock pulse edges appears.
With the objects of the invention in view there is also provided, a circuit configuration, including:
a data driver including an amplifier with a data input and a tristate output as a data output, the tristate output being switchable into a state of high output impedance by a deactivation signal;
a termination resistor connected to the data output;
a source for providing a medium level lying between a high validity level and a low validity level, the high validity level being higher than the low validity level;
the data output of the driver being connected, via the termination resistor to the source providing the medium level;
a buffer memory for simultaneously providing a current bit of a bit sequence and a directly following bit of the bit sequence; and
an activation circuit connected to the data input of the amplifier, the activation circuit responding to reference clock pulse edges and to the current bit and the directly following bit of the bit sequence for supplying an activation signal, the activation circuit supplying the activation signal such that, from a start of a preparation interval preceding a data item of a first binary value to a start of a following preparation interval, the activation signal has a level driving the data output to the high validity level and such that, from a start of a preparation interval preceding a data item of a second binary value to a start of a following preparation interval, the activation signal has a level driving the data output to the low validity level.
According to another feature of the invention, a comparison device is operatively connected to the activation circuit for comparing a binary value of a current data item and a binary value of a following data item; and the activation circuit keeps the level of the activation signal constant until, subsequent to the current data item, a preparation interval for the following data item starts and the binary value of the following data item differs from the binary value of the current data item.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and a circuit configuration for controlling a data driver, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.